In conventional signal processor designs using array multiprocessor architectures, operating speed has been impeded by the bandwidth of their internal bus structure. In conventional architectures, the communication between global memory and the processors cannot maintain maximum execution speed for several reasons. These reasons include the following: (1) transfer of data from the global memory to any of its processing elements must wait for the bus to be free to accept another transfer; (2) the memory address register must complete its read/write cycle in order to process another addressing request; and (3) only a single processor can initiate an address in a sequential mode of operation. These factors result in a significantly lower execution efficiency, which has been measured as low as 10 percent of rated throughput for some typical applications.
A system level solution to this problem has been developed in the form of a distributed memory addressing system (DMAS) that includes an n-port memory design with simultaneous addressing of each port through a special time division multiplexing (TDM) structure. This structure allows both horizontal and vertical addressing of locations in the entire n-port memory address space. The data from each port is transferred from the ports'memory interface (MIF) over dedicated serial lines to each processor interface (PIF) which transfers the data to the processor (CPU).
The design of a suitable PIF poses several challenges: (1) In order to minimize technology upgrade costs, it should be capable of interfacing with any commercial off-the-shelf digital signal processor CPU; (2) In order to minimize the CPU's addressing overhead, it should be able to rearrange data based on CPU-controlled addressing parameters; (3) it should be able to transfer data serially to global memory in a non-blocking fashion by using TDM.